1. Field of the Invention
This invention relates generally to non-volatile memory, and more particularly to a non-volatile memory controller capable of providing data integrity, including boot block data integrity, in a non-volatile memory system.
2. Description of the Related Art
Non-volatile memory is memory that retains stored data when not powered. Examples of non-volatile memory include Phase-change memory (PCM), Ferroelectric random access memory (FRAM), and flash memories. Because non-volatile memory retains stored data even when power to the memory is turned off, non-volatile memory is widely used in battery-driven portable devices. For example, flash memory often is utilized in digital audio players, digital cameras, mobile phones, and USB flash drives, which are used for general storage and transfer of data between computers.
Flash devices are designed to utilize two different types of technology, NOR technology and NAND technology. NOR flash devices have long erase and write times, but have an input/output (I/O) interface that allows random access to any location in the memory. As a result, NOR flash devices often are used for storing executable code, where the data that is stored is accessed in words or single instruction elements. Typically these accesses are to random locations because code execution often is non-sequential. This ability to fetch instructions from a flash device often is called “Execute in Place” (XIP).
NAND flash devices have faster erase/write times, higher density, and a lower cost per bit than NOR flash. However NAND flash devices have an I/O interface that allows only sequential access to data. As a result, NAND flash devices typically are used for storing data that is accessed in fixed sized pages. Typically these accesses are for a complete page of data. Although the read access time for a page is relatively slow for the first byte, the read access time for subsequent sequential bytes in the same page is extremely fast. Because of the inexpensive nature of the memory, NAND flash devices generally implement error correction code (ECC) functionality for block data integrity.
FIG. 1 is a diagram showing a prior art NAND flash memory based system 100 utilizing a NAND flash memory. The system 100 includes a processor 102, executing error correction software 104, and coupled to system memory 106. Also coupled to the processor 102 is a flash controller 108, which is coupled to flash memory 110. The flash controller 108 includes a plurality of registers 112 and a check code generator 114. The flash memory 110 includes a flash array 116 and a flash buffer 118.
In operation, the processor 102 utilizes the flash controller 108 to read and write data to the flash memory 110. For example, when writing data to the flash memory 110, the data is transferred from the system memory 106, though the flash controller 108, and into the flash buffer 118. When passing through the flash controller 108, the data passes through the check code generator 114, which calculates an error detection code that is appended to the data and stored with the data in the flash buffer 118. The data is then transferred from the flash buffer 118 and stored into the flash array 116.
When the data is later read from the flash memory 110, the flash controller 108 checks the data for errors using the check code generator 114. More particularly, when reading data from the flash memory 110, the data is transferred from the flash array 116 to the flash buffer 118. The flash controller 108 then reads the data from the flash buffer 118, passes the data through the check code generator 114, and stores the data into the system memory 106. While the data is being passed through the check code generator 114, the check code generator 114 calculates a new error detection code, which is compared to the error detection code that was stored with the data. If the new error detection code matches the stored error detection code, the data is error free. However, if the two error detection codes do not match, the error correction software 104 executing on the processor 102 attempts to correct the defects in the data, which is now stored in the system memory 106. This methodology works fine while the error correction software 104 is executing on the processor 102. However, the method does not perform properly when the error correction software 104 is not executing on the processor 102, such as at Power On Reset.
To address this issue, NAND flash memory vendors typically guarantee that the first page of data in the flash array 116 is free of defects. This eliminates the need for any ECC logic on the first page of data stored in the flash array 116. As a result, boot block data stored in the first page of data in the flash array 116 and used by the processor 102 during Power On Rest can be read into the processor 102 without first being checked for defects, as illustrated in FIG. 2.
FIG. 2 is a diagram showing the prior art NAND flash memory based system 100 during Power On Reset. Similar to above, the NAND flash memory based system 100 includes a processor 102 coupled to system memory 106 and a flash controller 108, which is coupled to flash memory 110. The flash controller 108 includes a plurality of registers 112 and a check code generator 114. The flash memory 110 includes a flash array 116 and a flash buffer 118.
During Power On Reset, boot block data must be loaded into the flash buffer 118 before any other software can execute on the processor 102. Thus, during Power On Reset the processor 102 is not executing error correction software. Consequently, error correction cannot occur prior to loading the boot block data. Fortunately, the boot block data is free of errors because it is stored in the first page of the flash array 116, which is guaranteed to be defect free. As a result, the processor 102 can execute the boot block data directly from the page buffer 118 without being first checked for errors.
As demand for greater functionality in devices has increased, so has demand for flash memory with greater storage capacity. To address such demands, multilevel-cell (MLC) flash memory has been developed. Single Level Cell (SLC) memory, as used in the prior flash devices described with reference to FIGS. 1 and 2, contain one bit of data in each memory cell. MLC memory cells contain two or more bits of data, thereby increasing the storage capacity of the device.
However, MLC flash memory is much less reliable than SLC flash memory. As such, MLC flash memory vendors no longer guarantee that the first page of data in the flash array will be free of defects. Consequently, the boot block data stored in the flash array is no longer guaranteed to be defect free, and thus cannot be safely read directly to the processor during Power On Reset without first being checked for errors.
In view of the foregoing, there is a need for systems and methods for checking the data integrity of boot block data from a flash memory device during Power On Reset. Because error correction logic is not running on the processor during Power On Reset, the systems and methods should not rely on system processor based error correction during Power On Reset.